Integrated circuits (ICs) may be designed to include embedded instruments for monitoring activities and conditions within the IC. Access to embedded IC instruments is typically achieved via the dedicated terminals of the IC's IEEE 1149.1 Test Access Port (TAP) interface.
FIG. 1 illustrates an example integrated circuit die 102 that includes functional circuits such as but not limited too, a microcontroller unit (MCU) 104 circuit core, a digital signal processor (DSP) 106 circuit core, memory circuit cores 108 and other functional digital or analog circuit cores 110. The IC's functional circuits are coupled together via an internal functional input and/or output (FIO) bus 112 to allow them to communicate with each other. The IC has external FIO signal terminals 114 to allow the functional circuits of IC 102 to communicate with functional circuits of other ICs.
FIG. 2 illustrates an example integrated circuit die that includes the functional circuits of die 102 plus the well known IEEE 1149.1 TAP 204, boundary register (BR) 206 and TAP input/output (TIO) interface 208. The TIO interface 208 includes TDI, TCK, TMS input signals and a TDO output signal. The TAP 204 responds to the TCK and TMS signals to input data from TDI and output data to TDO. If the boundary register 206 is selected for access it will shift data from TDI to TDO. During normal operation of the die 202, the boundary register couples the internal FIO bus signals 112 to the external FIO signals 114 to allow the die to functionally operate with other die. During boundary scan test mode using the well known 1149.1 Extest instruction, the boundary register isolates the internal FIO buss signals 112 from the external FIO signals 114. In the boundary scan Extest mode the boundary register can be operated by the TAP to perform interconnect testing between the external FIO signals 114 of die 202 and the FIO signals 114 of die connected to die 202.
FIG. 3 illustrates the TAP 204 of die 202 in more detail. The 1149.1 TAP includes, at minimum, a TAP state machine (TSM) 302, an instruction register 304, a Bypass Register 306, the Boundary Register 206 and a TDO output multiplexer circuitry 308. The TSM 304 operates according to the well known 16 state transition diagram of FIG. 4 in response to the TCK and TMS input signals to; (1) place the TAP in a Test Logic Reset state, (2) place the TAP in a Run Test/Idle state, (3) perform a scan operation to the instruction register from TDI to TDO, (4) to perform a data scan operation to the Bypass Register 308 from TDI to TDO or (4) perform a data scan operation to the Boundary Register 206 from TDI to TDO. The 1149.1 interface may include an optional TRST input, shown in dotted line, to reset the TSM and other TAP circuits. If the TRST input is not included, a Power Up Reset (POR) circuit 310 may be used to reset the TSM and other TAP circuits.
During instruction scan operations, the TSM outputs control (CTL) signals to the instruction register 304 and multiplexer circuitry 308. In response to the CTL signals the instruction register performs capture, shift and update operations. During the shift operation the instruction register shifts data from TDI to TDO via multiplexer 308.
During data scan operations, the TSM outputs CTL signals to the selected data register 306 or 206 and multiplexer 308. The instruction register output (IRO) bus enables the selected data register and controls multiplexer 308 to couple the TDO output of the selected data register to the TDO output of the die. In response to the CTL signals the selected data register performs capture, shift and update operations, except for the Bypass Register 306 which does not have update circuitry. During the shift operation the selected data register shifts data from TDI to TDO via multiplexer 308.
FIG. 5 illustrates an example integrated circuit die 502 that includes the functional circuits and IEEE 1149.1 TAP circuits of die 202 plus embedded instrumentation circuits 504. As seen, the embedded instrumentation circuits may exist as part of the functional circuits 104-110 of the die or they may exist as separate circuits on the die. In this example, access to the instrumentation circuits is achieved via the TAP of die 502. The instrumentation circuits may provide any type of operations on the die, including but not limited too, test operations, debug operation, trace operations, temperature monitoring operations and voltage monitoring operations.
FIG. 6 illustrates a first known example of how the TAP 204 may access the instruments 504 of die 502 of FIG. 5. In this example, each instrument 1−N is separately accessed between TDI and TDO by loading the TAP instruction register with an instruction that accesses a selected one of the instruments 1−N.
FIG. 7 illustrates a second known example of how the TAP 204 may access the instruments 504 of die 502 of FIG. 5. In this example, all instruments 1−N are accessed together in series between TDI and TDO by loading the TAP instruction register with an instruction that accesses all the serially connected instruments 1−N.
FIG. 8 illustrates a third known example of how the TAP 204 may access the instruments 504 of die 502 of FIG. 5. In this example, each instrument 1−N is interfaced to a segment insertion bit (SIB) 802-804 that can select its associated instrument for access or deselect its associated instrument from access. All the SIBs are serially connected together to form a data register. The SIB data register is selected between TDI and TDO by an instruction loaded in the TAP instruction register. When no instruments are selected the SIB data register consists only of a single bit for each SIB. For example if 5 SIBs exist in the SIB data register, the length of the data register will be 5 bits. When the bit of a SIB is loaded with a logic state for selecting its instrument, its instrument is included in the SIB data register between TDI and TDO. For example, if the bit of SIB 802 is set to a state that selects its instrument (i.e. Instrument 1), the SIB data register between TDI and TDO will be lengthened to included the length the register within Instrument 1. Using the SIBs, any of the instruments 1−N may be included into the SIB data register or excluded from the SIB data register. This instrumentation access example is the subject of a developing IEEE instrumentation access standard P1681. The concept of using SIB-like circuits (DSMs) for varying the length of a serial scan path was first described 1987 in U.S. Pat. No. 4,872,169.
FIG. 9 illustrates a device 902 comprising a stack of die 904-908 mounted upon a silicon interposer 910. The interposer 910 is further mounted to system substrate 912, such as, but not limited too, a smart phone printed circuit board (PCB), a PC PCB or another die. The die 904-908 in this example are designed using through silicon vias (TSV) 914. TSVs are connectivity paths formed between the top and bottom surfaces of the die. TSVs allow substrate signals to flow vertically up and down the die stack via the interposer 912 to provide input to and output from the circuitry in each die. The die circuitry of this example only contains functional circuitry as described in FIG. 1. Thus only FIO signals pass between the substrate 912 and the stacked die 904-908. The function of interposers is to spread connections from fine pitch contact points on one surface to wider pitch contact points on another surface. In this example, the fine pitch contact points on the bottom surface of die 904 are spread to match the wider pitch contacts points of the system substrate 912, via interposer 912.
FIG. 10 illustrates a device 1002 comprising a stack of die 1004-1008 mounted upon a silicon interposer 1010. The interposer 1010 is further mounted to system substrate 1012. As in the device 902 of FIG. 9, the die 1004-1008 in this example are designed using TSVs 914. The die circuitry of this example contains functional circuitry and TAP circuitry as described in FIGS. 2-4. Thus both FIO and TIO signals pass between the substrate 1012 and the stacked die 1004-1008. The TAP circuitry may provide access to embedded instruments on the die as described in FIGS. 5-8.
FIG. 11 illustrates a first method of providing the TIO (TCK, TMS, TDI and TDO) signals between the TAPs of die 1004-1008 and the substrate 1012. In this example, the substrate provides a dedicated TCK, TMS, TDI and TDO signal interface to each die so that each die TAP can be accessed separately. The problem with this method is that the substrate is required to include separate TIO busses for each die.
FIG. 12 illustrates a second method of providing the TIO signals between the TAPs of die 1004-1008 and the substrate 1012. In this example, the substrate provides a common TCK, TDI and TDO signal connections to each die TAP and separate a TMS signal to each die TAP. This example is commonly referred to as a STAR connection. To access the TAP of die 1004, its TMS signal becomes active to shift data in and out via TDI and TDO. To access the TAP of die 1006, its TMS signal becomes active to shift data in and out via TDI and TDO. To access the TAP of die 1008, its TMS signal becomes active to shift data in and out via TDI and TDO. The problem with this method is that the substrate is required to include a separate TMS signal for each die.
FIG. 13 illustrates a third method of providing the TIO signals between the TAPs of die 1004-1008 and the substrate 1012. In this example, the substrate provides common TCK and TMS signal connections to each die TAP, a TDI connection to die 1004 and a TDO connection to die 1008. The TDO signal of die 1004 is connected 1304 to the TDI signal of die 106 and the TDO signal of die 106 is connected 1306 to the TDI signal of die 1008. To access the serially connected TAPs of die 1004-108, the TCK and TMS signals become active to shift data into the serially connected die TAPs from the substrates TDI input to the TDO output. The problem with accessing device 1302 using this method is that serially connecting multiple TAPs together in a device is not compliant with the IEEE 1149.1 standard. IEEE 1149.1 expects a device to only have one instruction register and one bypass register connected between the devices TDI and TDO terminals.
The following disclosure describes a new method of providing instrumentation circuitry in devices that include stacked die mounted on interposers.